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RF2958
0
Typical Applications * IEEE 802.11b WLANs * Wireless Residential Gateways * Secure Communication Links Product Description
The RF2958 is a single-chip transceiver specifically designed for IEEE 802.11b applications. The part includes all required transceiver functions. The receiver includes: an LNA and downconverter; complete synthesizers and VCO's; direct conversion from IF receiver with variable gain control; quadrature demodulator; I/Q baseband amplifiers; and, on-chip baseband filters. For the transmit side, a QPSK modulator and upconverter are provided along with the synthesizer, VCO, and PA driver. A minimum number of external components are required, resulting in an ultra-compact low-cost radio design. Twocell or regulated three-cell (3.6V maximum) battery applications are supported by the part. The RF2958 is also part of a 2.4GHz chipset along with our high-efficiency GaAs HBT PA and the RF3002 Baseband Processor. Optimum Technology Matching(R) Applied
Si BJT Si Bi-CMOS InGaP/HBT
RX VGC RX Q RX I
2.4GHz SPREAD-SPECTRUM TRANSCEIVER
* High Speed Digital Links * Wireless Security * Digital Cordless Telephones
5.000 0.050
0.900 0.070
5.000 0.050
Shaded lead is pin 1.
Dimensions in mm.
3.400
0.400 0.050 TYP
-C-
SEATING PLANE 3.400
SCALE: NONE
0.500 TYP
0.100 M C 0.080 C
0.025 0.010
Package Style: QFN, 32-Pin, 5x5
GaAs HBT SiGe HBT GaN HEMT
VCC BB Q BYP I BYP TX Q
GaAs MESFET Si CMOS SiGe Bi-CMOS
Features * Complete IEEE802.11b Transceiver including VCOs
24 VREF
32
31
30
29
28
3rd Order Bes LPF
TX I
27
26
3rd Order Bes LPF
25
IF IN+ 1
3rd Order Bes LPF 3rd Order Bes LPF
* Small 32-pin Leadless Package * Minimal External Components Required * Low Receive Current * High Performance Super-het Architecture
IF IN- 2
IF Synth Analog
RF PLL Voltage Regulator
23 DIG REG
VCC IF 3
22 VCC PLL4
21 SCLK
RX IF Voltage Regulator 1 RX IF Voltage Regulator 2
SPI Serial Port Frac-N Digital P&R
20 SSB
R BIAS 4
D/A MUX
19 SDI
VCC RF2 5
VCC RF1 6
Digital Voltage Regulator LC Trap RF PLL Voltage Regulator
Ordering Information
18 MCLK
IF OUT- 7
RF Synth Analog
IF OUT+ 8
17 MODE0 9 TX VGC 10 RF OUT 11 VCC RF3 12 RF IN 13 LNA GS 14 VCC PLL1 15 PLL REG 16 MODE1
RF2958 RF2958TR13 RF2958 PCBA
2.4GHz Spread-Spectrum Transceiver 2.4GHz Spread-Spectrum Transceiver (Tape & Reel) Fully Assembled Evaluation Board Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
Functional Block Diagram
RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA
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RF2958
Absolute Maximum Ratings Parameter
Supply Voltage Control Voltages Input RF Level Operating Ambient Temperature Storage Temperature
Refer to "Handling of PSOP and PSSOP Products" on page 16-15 for special handling information.
Rating
-0.5 to +3.6 -0.5 to +3.6 +12 -40 to +85 -40 to +150
Unit
VDC VDC dBm C C
Refer to "Soldering Specifications" on page 16-13 for special soldering information.
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Parameter
Receiver LNA/RF
RF Frequency Range IF Frequency Range Voltage Gain - High
Specification Min. Typ. Max.
2400 363 32 (20dB power) -1 (-13dB power) 2500 385 38 (26dB power) +5 (-7dB power)
Unit
Condition
VCC =3.0V, T=+25C, MCLK=44MHz, unless otherwise specified
Voltage Gain - Low
Noise Figure - High Gain Noise Figure - Low Gain Input IP3 - High Gain Input IP3 - Low Gain Input P1dB - High Gain Input P1dB - Low Gain Input Return Loss Output Impedance Image Rejection
35 (23dB power) +2 (-10dB power) 4 32
MHz MHz dB
dB
374MHz 11MHz LNA/mixer voltage gain (Note: into output impedance). LNA/mixer/SAW filter voltage gain. LNA GS=1 LNA/mixer voltage gain. LNA GS=0
-23 +8 -30 -2 10 750 30
dBm dBm dBm dBm dBm dBm dB dB
Z0 =50
Receiver IF VGA/Baseband
IF Frequency Range IF Input Impedance Voltage Gain - High Voltage Gain - Low Gain Accuracy Gain Response Time Gain Flatness Input Referred Noise Input V1dB Output Distortion Output Voltage Output V1dB -0.25 374 750 70 4 3 300 +0.25 11 500 1.0 0.75 1.25 MHz dB dB dB ns dB uVRMS mVP-P % VP-P VP-P
VGC =1.25V (measured to single-ended output) VGC =1.95V (measured to single-ended output) For a given RX VGC voltage, the measured gain should lie within 3dB of ideal Measured with a DC step from 1.3V to 1.8V to 90% final value (within 1dB) 374MHz 11MHz, relative to gain at 374MHz Measured into the IF VGA pin. 1dB compression of IF strip. Measured at input to RF3002 single-ended. Single-ended.
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Parameter
Receiver IF VGA/Baseband, cont'd
Group Delay Filter Rejection Output Impedance I/Q Magnitude Error I/Q Phase Error I/Q DC Offset DC Step VREF VREF Output Current 15 20 0.35 3.0 10 40 1.75 ns dB dB mV mV V mA Transfer function - 3 pole Bessel at 9MHz f<1MHz
Specification Min. Typ. Max.
Unit
Condition
1.65 1.0
1.7
SQRT [(VOUTI -VREF)^2+(VOUTQ -VREF)^2)] VGC step 1.3V to 1.8V, PIN =-50dBm 3% variation Source
Transmitter Modulator/Baseband
I/Q Magnitude Error I/Q Phase Error Input Signal (Single-Ended) Input Signal Magnitude Input P1dB Voltage Gain to IF Output Voltage Output SNR Carrier Leakage 0.35 3.0 200 282 566 4 448 6 564 32 8 710 -20 550 20 0 17 300 30 -25 dB mVP-P mVP-P mVP-P dB mVP-P dB dBc mVP-P uVRMS dB dB ns dB dBm mVP-P dBm dBm
SQRT(I^2+Q^2) 6dB from input Measure from complex magnitude to IFVP-P Connected to SAW filter Single sideband modulation 6dB from max input Measured in 11MHz bandwidth at 2.442GHz upconverter gain >12dB TX VGC at 1.3V TX VGC at 1.9V Measured with 300mV change in gain on TXVGC to 90% of final POUT. FLO =2048MHz to 2110MHz 802.11b output with 7dB to 20dB gain (needed for +20dBm POUT). TXVGC at 1.3V Meeting 802.11b Spectral Mask
VGA Driver/Upconverter
Input P1dB Input Referred Noise Minimum Gain Maximum Gain Gain Response Time Image Rejection RF LO Leakage Output Voltage Minimum Output Power Maximum Output Power
-36 1000 -12
0
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Parameter
Digital Input Specifications
Apply to pins: SSB, SDI, SCLK, MODE0, MODE1 Input High Voltage (VIH) Input Low Voltage (VIL) Input High Static Current (IIH) Input Low Static Current (IIL) Reset Time Apply to pins: SSB, SDI, SCLK Input Setup Time (TSU)* Input Hold Time (THLD)* Input Rise/Fall Time (TRFI) Input Clock to Select Time (TCS) Input Clock Pulse Width High (TCWH) Input Clock Pulse Width Low (TCWL) PLL Recalibration Pulse Width (TRC) 0.7VDD 0.3VDD 5 5 50 5 5 5 5 22 22 1/fr V V A A s ns ns ns ns ns ns s For fr=22MHz, TRC is 45.5ns minimum
Specification Min. Typ. Max.
Unit
Condition
Exiting Reset mode or using SPI Reset
Digital Driver Output
Apply to pin: SDI (output mode) Output High Voltage (VOH) Output Low Voltage (VOL) Output Rise/Fall Time (TRFO) Output Current Source (|IOH|) Output Current Sink (|IOL|) 0.8VDD 0.2VDD 5 3.8 10 V V ns mA mA With 1mA load With 1mA load With 20pF maximum load capacitance measured from 10% to 90% of output voltage Output at (VDD -0.3V) Output at 0.3V MCLK can be driven DC-coupled by a CMOS clock oscillator with rail-to-rail outputs. Other oscillator configurations may require AC-coupling.
MCLK Input (AC-Coupled)
Apply to pin: MCLK Peak-to-Peak Input Voltage (VP-P) DC Bias at MCLK (MCLK_DC)
500 0.6 1.1
mV V
Specification Valid Range
Temperature -30 +70 C Supply Voltage 2.7 3.0 3.6 V Transmit Current 50 68 80 mA Receive Current 30 52 60 mA Idle Current 5 28 40 mA Reset Current 1 2 mA Hibernate Current 0.2 0.5 mA *Setup and Hold Times are measured from the time where the waveforms cross VDD/2.
MODE0=0, MODE1=1 MODE0=1, MODE1=0 MODE0=0, MODE1=0 MODE0=1, MODE1=1
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Digital Timing Specifications
TCS SSB TCWH TCWL
SCLK MSB SDI TSU Internal Recal pulse THLD TRC LSB
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Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pkg Base Function IF IN+ IF INVCC IF R BIAS VCC RF2 VCC RF1 IF OUTIF OUT+ TX VGC RF OUT VCC RF3 RF IN LNA GS VCC PLL1 PLL REG MODE1 MODE0 MCLK SDI SSB SCLK VCC PLL4 DIG REG VREF Q BYP TX Q I BYP TX I VCC BB RX Q RX I RX VGC GND ESD Description
Differential input from IF SAW filter. See application schematic for matching circuit. See pin 1. Power supply for IF circuitry. Provide 330pF bypass capacitor close to this pin. Bandgap voltage reference for on-chip biasing. Install a 22.1k, 1% resistor from this pin to ground. Power supply for TX and RX bias, LO buffers and mixers. Provide 6pF bypass capacitor close to this pin. See pin 5. Differential output to IF SAW filter. See application schematic for matching circuit. See pin 7. TX analog gain control. Depending on desired operation mode, transmitter gain can be controlled through this pin or the three-wire digital interface. This pin can also provide a bias voltage to an external PA. See theory of operation for details. TX PA driver output. Power supply for LNA and TX output driver. Power should be connected to this pin through an inductor or a long 50 transmission line RF-shorted with a 6pF capacitor at the other end. RX input from antenna. Gain select pin for the internal LNA. High-gain operation is selected when this pin is a logic `1'. Power supply for the PLL RF LO synthesizer. Provide 0.01F and 6pF bypass capacitors close to this pin. Internal PLL regulator output. Bypass with 10nF capacitor. Do not connect to VCC or ground. Controls operational state of the device. See Theory of Operation section for details. See pin 16. Reference oscillator for the PLL synthesizer. Data signal for the synchronous three-wire digital control interface. Chip select signal for the synchronous three-wire digital control interface. Clock signal for the synchronous three-wire digital control interface. Power supply for the PLL IF LO synthesizer. Provide 0.01F and 330pF bypass capacitors close to this pin. Internal digital regulator output. Bypass with 10nF capacitor. Do not connect to VCC or ground. I/Q DC reference voltage for the baseband processor. This pin should be connected to a high impedance on the baseband processor. Baseband differential input signal for the TX quadrature channel. For single-ended applications, bypass to ground with a 0.01F capacitor. Baseband input signal for the TX quadrature channel. Baseband differential input signal for the TX in-phase channel. For single-ended applications, bypass to ground with a 0.01F capacitor. Baseband input signal for the TX in-phase channel. Power supply for baseband circuitry. Provide 0.01F bypass capacitor close to this pin. Baseband output signal for the RX quadrature channel. Baseband output signal for the RX in-phase channel. Analog gain control for the RF IF amplifier. Device ground. Connect directly to PCB ground plane. All pins except pin 12 are provided with electrostatic discharge protection to 3kV using the human body model.
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Pin Out
RX VGC VCC BB RX I Q BYP 25 24 VREF 23 DIG REG 22 VCC PLL4 21 SCLK 20 SSB 19 SDI 18 MCLK 17 MODE0 9 TX VGC 10 RF OUT 11 VCC RF3 12 RF IN 13 LNA GS 14 VCC PLL1 15 PLL REG 16 MODE1 I BYP 27 RX Q TX Q 26 TX I 28
32 IF IN+ 1 IF IN- 2 VCC IF 3 R BIAS 4 VCC RF2 5 VCC RF1 6 IF OUT7
31
30
29
IF OUT+ 8
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Detailed Functional Block Diagram
RX VGC VCC BB Q BYP 25 I BYP 27 RX Q TX Q 26
3rd Order Bes LPF
RX I
32
31
30
29
28
3rd Order Bes LPF
IF IN+ 1
3rd Order Bes LPF 3rd Order Bes LPF
TX I
24 VREF
RF PLL Voltage Regulator
IF IN- 2
IF Synth Analog
23 DIG REG
VCC IF 3
22 VCC PLL4
21 SCLK
RX IF Voltage Regulator 1 RX IF Voltage Regulator 2
SPI Serial Port Frac-N Digital P&R
20 SSB
R BIAS 4
D/A MUX
19 SDI
VCC RF2 5
VCC RF1 6
Digital Voltage Regulator LC Trap RF PLL Voltage Regulator
18 MCLK
IF OUT- 7
RF Synth Analog
IF OUT+ 8
17 MODE0 9 TX VGC 10 RF OUT 11 VCC RF3 12 RF IN 13 LNA GS 14 VCC PLL1 15 PLL REG 16 MODE1
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Theory of Operation
The RF2958 is a single-chip transceiver designed specifically for IEEE 802.11b wireless LAN applications. In addition to typical transceiver functions of RF conversion of both the transmit and receive signals, the RF2958 incorporates a lownoise amplifier (LNA) and a dual phase-locked loop (PLL) frequency synthesizer to reduce end-product component count and to simplify integration into end-products. The RF2958 uses a superheterodyne frequency conversion architecture in both the transmit and receive signal paths for superior performance in 802.11b applications. It also incorporates power conservation functionality to increase battery life in portable and mobile applications. When used with the RF3002 baseband processor and RF5189 power amplifier (PA), the RF2958 is part of a complete PHY solution for 802.11b applications (see figure below, 2.4GHz IEEE 802.11b Chipset Block Diagram).
fC = 374 MHz BW = 20 MHz
RF3002 RF2958
RXVGC DAC CCA RX VGC
RX VGC
RF5189
ANT SEL RX I VREF
I IN ADC Demodulator
CCA LNA GS
802.11 Preamble/ Header
fC = 2450 MHz BW = 100 MHz
TX/RX SWITCH
REF
RX Q TX VGC TX I
Data Converter Reference
RX DATA
ANTENNA DIVERSITY SWITCH
TX PE RX PE
Q IN ADC
RX RDY DATA CLK
TX VGC DAC
Control Port
Mode Control
SPI TX RDY
TX Q
I OUT DAC
TX DATA
Modulator 802.11 Preamble/ Header
Tx Length Tx Signal Service
Serial Data Interface RF PLL PLL/Power Control Registers IF PLL
Q OUT DAC
RX PE TX PE M CLK
SDI
SYSTEM ARCHITECTURE The overall system architecture is based around a superheterodyne conversion process. For the transmitter side, the baseband in-phase (I) and quadrature (Q) signal components are converted to an intermediate frequency (IF) of 374MHz. An external SAW filter is used to filter out undesired spurious frequencies. The IF is then converted to the overthe-air radio frequency (RF) between 2.412GHz and 2.483GHz using low-side injection. The RF output drives a PA to amplify the signal to the desired power level at the antenna. Generally the PA is followed by a TX/RX switch and a band pass filter which eliminates the undesired sideband resulting from the mixing process before broadcasting the signal through the antenna. The receiver is the inverse of this process. The signal from the antenna passes through the band pass filter, which is in this case acting as a pre-selection filter. The received signal passes through the integrated LNA and is converted to an IF of 374MHz. The signal then passes through a SAW filter, which acts to reject adjacent channels as defined by the 802.11 standard. Due to the bandwidth of this filter, adjacent channels must be at least 20MHz apart. The filtered IF signal is then downconverted to baseband I and Q components. The local oscillators required by the mixing process are generated by internal IF and RF PLL frequency synthesizers. These are controlled through a three-wire serial data interface.
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GENERAL APPLICATION INFORMATION This part is used at high frequencies. Proper attention to layout and component selection is critical in order to achieve the specified performance. Values for DC blocking capacitors and power supply bypass capacitors should be selected so that they are series self-resonant at the frequency of operation. In addition, transmission line techniques should always be used on signal lines at RF frequencies, and may be required on signal lines at IF frequencies if connections are long with respect to wavelength. The RF2958 should be powered from regulated supply. If not sharing this supply with the MCLK oscillator, the MCLK oscillator should also be powered from a well-regulated supply. Avoid sharing the RF2958 and MCLK oscillator supplies with the baseband processor and/or MAC. Power supply bypassing of VCC lines for the PLL is critical in order to minimize the effects of power supply noise on phase noise performance. In addition to RF/IF bypassing, these lines should be bypassed with low-frequency capacitors. A value of 0.01F is sufficient for most applications, but performance should be verified by looking at a modulated signal on a vector signal analyzer or a constant signal on a spectrum analyzer or phase noise test set. Since this is a mixed-signal device, care should be taken to separate traces connecting to digital circuits from those connecting to analog circuits. Power supply bypassing is important to keep the noise contributions of digital circuits to a minimum. It is generally better to start with more bypassing than you think you need, then remove components and reevaluate performance. ENABLE/DISABLE MODES Operation of the device is controlled by the MODE0 and MODE1 pins according to the following truth table.
MODE0 0 0 1 1 MODE1 0 1 0 1 Function Idle Transmit Enable Receive Enable Reset
When switching between modes, ensure that MODE0 and MODE1 are high for less than three master clock cycles to avoid inadvertently entering reset modes. To enter reset mode, ensure that MODE0 and MODE1 are high for at least five master clock cycles. In Idle mode, the IF and RF PLLs are locked and the baseband circuitry is powered; everything else is disabled. In Reset mode, the voltage regulators for the digital circuitry inside the part are enabled; everything else is disabled. Additionally, there is a hibernate mode in which everything is disabled. This mode is entered by writing the value 8h to Register 0 while in hibernate mode. The MODE0 and MODE1 pins should be held high while in hibernate mode. To exit this mode, toggle the states of one or both MODE pins. All registers will need to be reprogrammed on exiting hibernate mode. RECEIVER Front End LNA/Mixer The LNA/Mixer provides 35dB conversion gain to IF in high-gain mode to detect weak signals at the antenna. In low-gain mode, the LNA/Mixer provides 2dB conversion gain. The LNA GS pin selects gain mode. When LNA GS is high, the part is in high-gain mode. The mixer output is connected to the IF OUT pins as a differential signal for connecting to an external SAW filter. Proper matching at the input and output of the SAW filter is essential for maintaining performance through the system. The IF input and output differential impedances are 750 nominal. The same filter is used for transmitter and receiver. Internal switches control which signal is present at the SAW filter. If AC-coupling is required for the SAW filter, use values less than 150pF to ensure that switching speed will not be seriously degraded.
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IF/Baseband The filtered IF signal is processed through a variable gain amplifier controlled through the RX VGC pin. The IF signal is then downconverted to baseband I and Q signals, which are then filtered on-chip with third order Bessel filters. The IF-to-baseband conversion gain range is 4dB to 72dB depending on the voltage present on the RX VGC pin. The gain slope is negative over a range of 1.2V to 2.0V. The single-ended I and Q outputs should be DC-coupled to the baseband processor. The DC reference voltage should be provided to the baseband processor through the VREF pin to eliminate the potential for a signal blocker at DC. TRANSMITTER The I and Q inputs are differential. To use single-ended inputs, place 0.01F capacitors at the I BYP and Q BYP pins. The inputs should be DC-coupled from the baseband processor. In order to improve carrier suppression at RF, the DC reference voltage should be provided to the baseband processor through the VREF pin. The baseband input signals are filtered on-chip using third order Bessel filters for spectral shaping. The signals are then complex upconverted to IF. The IF mixer output is amplified and connected to the IF OUT pins as a differential signal for connecting to the external SAW filter as described above. The differential signal from the SAW filter is then amplified using a variable gain amplifier. The gain of this amplifier can be controlled either through the analog TX VGC pin or digitally from the baseband processor or MAC, depending on application. The signal is then upconverted to the desired RF output frequency and amplified to a level appropriate to drive a PA to the desired output level at the antenna. In order to further extend battery life, the TX VGC pin can be used to control the bias of the external PA. If the user of the end-product determines that he/she does not require full output power, the PA bias and the gain of the IF variable gain amplifier can be controlled by the RF2958 to reduce the current consumption of the PA, thereby increasing battery life. Contact RFMD Applications Engineering for guidance on implementing this feature. DUAL FREQUENCY SYNTHESIZER IF LO PLL The IF PLL is an integer-N PLL nominally programmed to a center frequency of 748MHz. This frequency is divided by two at the IF converter. A 44MHz oscillator is required to provide the PLL reference frequency through the MCLK pin. See the Register Details and Serial Data Interface sections for details on programming. RF LO PLL The RF LO PLL is a fractional-N PLL programmed to an appropriate frequency to convert the 374MHz IF to the desired RF channel. The nominal step size is 22MHz with a fractional modulus of 224. The 44MHz reference frequency is divided to the appropriate step size. See the Register Details and Serial Data Interface sections for details on programming. Note: To ensure proper operation of the PLLs, program Register 12 [17:16] to `11b'. All other bits in Register 12 should be set to `0'.
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RF2958
SERIAL DATA INTERFACE A three wire serial data interface allows user programming of the internal control registers in the RF2958. The serial data interface consists of the serial select (SSB), serial data in (SDI) and serial clock (SCLK) pins. The SDI is a bi-directional pin, by default it is configured as an input to the serial interface, but during a read session it is used as an output. The first bit in a serial transfer (the MSB) is the read/write (R/W) bit. R/W = 1 for a read, and R/W = 0 for a write. The figure below shows a timing diagram for a serial transfer to the RF2958 serial data interface. The serial select (SSB) pin is normally high. A serial transfer is initiated by taking SSB low. The address and data bits on the serial data in (SDI) pin are shifted in on rising edges of the serial clock (SCLK) pin, MSB first. The data is latched and changes take effect on the falling edge of the clock pulse corresponding to the last (18th) data bit in the addressed register. If the transfer is interrupted, such that the 18th data bit clock pulse does not occur, then no data is written to the register. When the synthesizers are programmed, an internal pulse is generated alerting the synthesizer that a new setting is required. In order to guarantee that this internal pulse is long enough, the time between the falling edge of the last serial clock pulse and the rising edge of SSB must be at least 1/fr. The RF2958 can be reset to its power on condition (including register defaults) by writing `011111b' plus 18 don't care bits to the serial data interface. The reset is actually performed when the SSB is raised after the write. Although this command can be performed during any settings of the MODE0 and MODE1 pins, care should be taken to ensure that the registers are reprogrammed in a sufficient time to perform any transmit or receive operations.
Serial Write SSB SDI SCLK Serial Read SSB SDI SCLK
rw=1 addr4 addr3 addr1 addr0 data17 data16 data1 data0 rw=0 addr4 addr3 addr1 addr0 data17 data16 data1 data0
sdi pin direction - input
sdi pin direction - output
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REGISTER DETAILS The individual registers and bits are described below. A write instruction to address 11111 causes global reset. All programming values are binary unless otherwise specified. Configuration Register 1 (CFG1)-Address 00000 Location Bit Name Default
CFG1(17:16) CFG1(15:14) reserved REF_SEL(1:0) 00 00
Function
Reserved, program to zero (0) Reference Divider Value 0 0 Divide by 2 1/2 high, 1/2 low 0 1 Divide by 3 1/3 high, 2/3 low 1 0 Divide by 44 1/44 high, 43/44 low 1 1 Divide by 1 (bypass) Sleep Mode Current 0=nominal sleep mode current 1=very low sleep mode current RF VCO Regulator Enable 0=disabled 1=enabled IF VCO Regulator Enable 0=disabled 1=enabled IF VGA Regulator Enable 0=disabled 1=enabled
CFG1(3)
HYBERNATE
0
CFG1(2)
RF_VCO_ REG_EN IF_VCO_ REG_EN IF_VGA_ REG_EN
1
CFG1(1)
1
CFG1(0)
1
IF PLL Register 1 (IFPLL1)-Address 00001 Location Bit Name Default
IFPLL1(17) PLL_EN1 0
Function
IF PLL Enable 0=disabled 1=enabled IF PLL KV Calibration Enable 0=disabled 1=enabled IF PLL Coarse Tune Enable 0=VCO coarse tuning system is disabled 1=VCO coarse tuning system is enabled IF PLL Loop Filter Bypass 0=Internal loop filter is used 1=Internal loop filter is bypassed and External loop filter is used IF PLL Charge Pump Leakage Current 0=minimum value 1=2xminimum value IF PLL Phase Detector Polarity 0=positive, VCO frequency increases with increasing tuning voltage 1=negative, VCO frequency decreases with increasing tuning voltage IF PLL Auto Calibration Enable 0=disabled 1=enabled IF PLL Lock Detect Enable 0=disabled 1=enabled IF PLL Prescaler Modulus 0=4/5 Mode 1=8/9 Mode Reserved, program to zero (0) IF VCO Coarse Tuning Voltage LPF_V1=int (coarse tuning voltage/VDD)x16
IFPLL1(16)
KV_EN1
0
IFPLL1(15)
VTC_EN1
1
IFPLL1(14)
LPF1
0
IFPLL1(13)
CPL1
0
IFPLL1(12)
PDP1
1
IFPLL1(11)
AUTOCAL_ EN1 LD_EN1
0
IFPLL1(10)
0
IFPLL1(9)
P1
0
IFPLL1(8:4) IFPLL1(3:0)
Reserved DAC1(3:0)
00000 3h
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IF PLL Register 2 (IFPLL2)-Address 00010 Location Bit Name Default
IFPLL2(17:16) IFPLL2(15:0) Reserved IF_N(15:0) 0 22h Reserved, program to zero (0) IFPLL divide-by-N value
Function
IF PLL Register 3 (IFPLL3)-Address 00011 Location Bit Name Default
IFPLL3(17) IFPLL3(16:8) IFPLL3(7:4) IFPLL3(3:0) Reserved DN1(16:8) CT_DEF1(3:0) KV_DEF1(3:0) 0 1FFh 7h 8h
Function
Reserved, program to zero (0) IF VCO KV Calibration, delta N value (signed 2's complement) DeltaF=DN1/(Fr) IF VCO Coarse Tuning Value IF VCO KV Calibration, default value
RF PLL Register 4 (RFPLL1)-Address 00100 Location Bit Name Default
RFPLL1(17) PLL_EN 0
Function
RF PLL Enable 0=disabled 1=enabled RF PLL KV Calibration Enable 0=disabled 1=enabled RF PLL Coarse Tune Enable 0=VCO coarse tuning system is disabled 1=VCO coarse tuning system is enabled RF PLL Loop Filter Bypass 0=Internal loop filter is used 1=Internal loop filter is bypassed and External loop filter is used RF PLL Charge Pump Leakage Current 0=minimum value 1=2xminimum value RF PLL Phase Detector Polarity 0=positive, VCO frequency increases with increasing tuning voltage 1=negative, VCO frequency decreases with increasing tuning voltage RF PLL Auto Calibration Enable 0=disabled 1=enabled RF PLL Lock Detect Enable 0=disabled 1=enabled RF PLL Prescaler Modulus 0=8/9 Mode 1=8/10 Mode Reserved, program to zero (0) RF VCO Coarse Tuning Voltage LPF_V1=int (coarse tuning voltage/VDD)x16
RFPLL1(16)
KV_EN
0
RFPLL1(15)
VTC_EN
1
RFPLL1(14)
LPF
0
RFPLL1(13)
CPL
0
RFPLL1(12)
PDP
1
RFPLL1(11)
AUTOCAL_EN
0
RFPLL1(10)
LD_EN
0
RFPLL1(9)
P
0
RFPLL1(8:4) RFPLL1(3:0)
Reserved DAC(3:0)
00000 3h
RF PLL Register 5 (RFPLL2)-Address 00101 Location Bit Name Default
RFPLL2(17:6) RFPLL2(5:0) N2(11:0) NUM2(23:18) 5Eh 0 RF PLL Divide By N Value RF PLL Numerator Value
Function
RF PLL Register 6 (RFPLL3)-Address 00110 Location Bit Name Default
RFPLL3(17:0) NUM2(17:0) 0 RF PLL Numerator Value
Function
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RF2958
RF PLL Register 7 (RFPLL4)-Address 00111 Location Bit Name Default
RFPLL4(17) RFPLL4(16:8) RFPLL4(7:4) RFPLL4(3:0) Reserved DN(8:0) CT_DEF(3:0) KV_DEF(3:0) 0 145 h 7h 8h
Function
Reserved, program to zero (0) RF VCO KV Calibration, delta N value (signed 2's complement) DN=(deltaF/Fr)*256 RF VCO Coarse Tuning Value RF VCO KV Calibration, default value
Calibration Register 8 (CAL1)-Address 01000 Location Bit Name Default
CAL1(17:13) CAL1(12:8) CAL1(7:3) CAL1(2:0) TVCO(4:0) TLOCK(4:0) M_CT_VALUE (4:0) LD_WINDOW (2:0) 0Fh 07h 08h 2h
Function
VCO1 Warm-up Time TVCO1=(approximate warm-up time)x(Fr/32) VCO1 Tuning Gain Calibration, approximate lock time TLOCK1=(approximate lock time)x(Fr/128) VCO1 Coarse Tune Calibration Reference clock averaging time M_CT_VALUE=(averaging time)x(Fr/32) Lock Detect Resolution 0 through 7
TXRX Register 9 (TXRX1)-Address 01001 Location Bit Name Default
TXRX1(17) RXDCFBBYPS 0
Function
Receiver DC Removal Loop 0=Enable DC Removal Loop 1=Disable DC Removal Loop 00 External TXVGC Controls VGA 01 External TXVGC Controls VGA 10 Internal Control of VGA from Register TXVGC(4:0) 11 Internal Control of VGA from Power Control Transmit Variable Gain Select 0h-1Fh High gain to low gain Receive Baseband Low Pass Filter Bandwidth Selection 000=Wide Bandwidth 111=Narrow Bandwidth Transmit Baseband Low Pass Filter Bandwidth Selection 000=Wide Bandwidth 111=Narrow Bandwidth Switches Between Single-Ended and Differential Mode 0=Single-ended mode 1=Differential mode Input Buffer Enable TX 0=Input Buffer Controlled by TXEN 1=Input Buffer Controlled by BBEN Internal Bias Enable 0=Disabled - External Bias Required 1=Enabled - Internal Bias Enabled TX Baseband Filters Bypass 0=Not Bypassed 1=Bypassed
TXRX1(16:15)
PCONTROL (1:0)
00
TXRX1(14:10) TXRX1(9:7)
TXVGC(4:0) RXLPFBW (2:0) TXLPFBW (2:0) TXDIFFMODE
00000 010
TXRX1(6:4)
010
TXRX1(3)
0
TXRX1(2)
TXENMODE
0
TXRX1(1)
INTBIASEN
0
TXRX1(0)
TXBYPASS
0
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RF2958
Power Control Register 10 (PCNT1)-Address 01010 Location Bit Name Default
PCNT1(17:15) MID_BIAS(2:0) 000
Function
PCNT1(14:9)
P_DESIRED (5:0) PC_OFFSET (5:0) TX_DELAY (2:0)
000000
PCNT1(8:3)
000000
PCNT1(2:0)
000
Used to setup the voltage provided by the PA_BIAS AMPLIFIER to determine the BIAS VOLTAGE to provide to the PA when the desired output power is MID_POWER. The MID_BIAS selection will select a VOUT on PBIAS between 1.6V and 2.6V. User selectable desired output power at antenna. The 5 MSB's are integer portion in dBm. The LSB is 0.5dBm. Example: +19.5dBm is represented by 100111. User programmable offset to adjust to process/board variations in the power control loop. This is a 2's-complement value with the LSB equal to 0.5dB. User programmable delay to allow a single TX_PE line to be used to enable the BBP and the radio function. Programmable in 0.5us increments from 0us to 3.5us.
Power Control Register 11 (PCNT2)-Address 01011 Location Bit Name Default
PCNT2(17:12) MAX_POWER (5:0) MID_POWER (5:0) 000000
Function
PCNT2(11:6)
000000
PCNT2(5:0)
MIN_POWER (5:0)
000000
User programmable MAX output power provided when PABIAS=2.6V. This allows the power control function to be customized for various PA's. The 5 MSB's are integer portion in dBm. The LSB is 0.5dBm. User programmable MAX output power provided when PABIAS=MID_BIAS. This allows the power control function to be customized for various PA's. The 5 MSB's are integer portion in dBm. The LSB is 0.5dBm. User programmable MAX output power provided when PABIAS=1.6V. This allows the power control function to be customized for various PA's. The 5 MSB's are integer portion in dBm. The LSB is 0.5dBm.
VCOT1 Register 1 (VCOT1)-Address 01100 Location
VCOT1(17)
Bit Name
AUX
Default
0
Function
IF VCO Band Current Compensation 0=disabled 1=enabled RF VCO Band Current Compensation 0=disabled 1=enabled Reserved, program to zero (0)
VCOT1(16)
AUX1
0
VCOT1(15:0)
Reserved
0
Test Register 1 (TEST)-Address 11011
This is a test register for internal use only.
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RF2958
Demodulator Gain versus RXVGC versus Temperature
80.0 70.0 60.0 Demodulator Gain vs. RXVGC @ -30C Demodulator Gain vs. RXVGC @ 25C Demodulator Gain vs. RXVGC @ 70C 100.0 1000.0
Demodulator Input V1dB versus Gain versus Temperature
IV1dB vs. Gain @ -30C IV1dB vs. Gain @ 25C IV1dB vs. Gain @ 70C
Demodulator Gain (dB)
50.0 40.0 30.0 20.0 10.0 0.0 -10.0 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
Input Voltage (mV P-P)
10.0
1.0
0.1 -10.0 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0
RXVGC (V)
Demodulator Voltage Gain (dB)
Output V1dB versus Gain versus Temperature
10000.0 OV1dB vs. Gain @ -30C OV1dB vs. Gain @ 25C OV1dB vs. Gain @ 70C 0.20 0.00 -0.20 -0.40
Demodulator Magnitude and Phase Error
0.20
0.15
I/Q Phase Error ()
0.10 -0.60 -0.80 0.05 -1.00 -1.20 0.00 -1.40 -1.60 Phase Error vs. Frequency -1.80 Magnitude Error vs. Frequency -0.10 -4.0 -2.0 0.0 2.0 4.0 6.0 8.0 10.0 12.0 -0.05
1000.0
100.0 -10.0 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0
-2.00 -12.0 -10.0 -8.0 -6.0
Demodulator Voltage Gain (dB)
Baseband Frequency (Hz)
TX/RX Baseband Filter Response
5 0 -5 -10 -15 -20 -25 -30 -35 -40 1.00E+00
000 100 001 101 010 110 011 111
Voltage Gain (dB)
1.00E+01
1.00E+02
Frequency (MHz)
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I/Q Magnitude Error (dB)
Output V1dB (mV P-P)
RF2958
Upconverter Gain versus Analog TXVGC
30.0 Upconverter Gain vs. TXVGC @ -30C Upconverter Gain vs. TXVGC @ 25C Upconverter Gain vs. TXVGC @ 70C 30.0 Upconverter Gain vs. TXVGC @ -30C 25.0 Upconverter Gain vs. TXVGC @ 25C Upconverter Gain vs. TXVGC @ 70C
Upconverter Gain versus Digital TXVGC
25.0
20.0
20.0
Voltage Gain (dB)
15.0
Voltage Gain (dB)
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5
15.0
10.0
10.0
5.0
5.0
0.0
0.0
-5.0
-5.0
-10.0
-10.0 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0
TXVGC (V)
TXVGC Value
Upconverter P1dB versus Analog TXVGC
8.0 8.0
Upconverter P1dB versus Digital TXVGC
6.0
6.0
4.0
4.0
Output P1dB (dBm)
2.0
Output P1dB (dBm)
Upconverter Output P1dB vs. TXVGC @ -30C Upconverter Output P1dB vs. TXVGC @ 25C Upconverter Output P1dB vs. TXVGC @ 70C 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5
2.0
0.0
0.0
-2.0
-2.0
-4.0
-4.0 Upconverter Output P1dB vs. TXVGC @ -30C -6.0 Upconverter Output P1dB vs. TXVGC @ 25C Upconverter Output P1dB vs. TXVGC @ 70C -8.0 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0
-6.0
-8.0
TXVGC (V)
TXVGC Value
Modulator Magnitude Error and Image Suppression
36.50 Image Suprression vs. Frequency 36.00 35.50 Magnitude Error vs. Frequency 0.05 0.10
35.00 34.50 34.00 33.50 33.00 32.50 32.00 31.50 -12.0 -10.0 -8.0 -6.0 -4.0 -2.0 0.0 2.0 4.0 6.0 8.0 -0.15 10.0 12.0 -0.10 -0.05 0.00
Baseband Frequency (MHz)
11-280
I/Q Magnitude Error (dB)
Image Suppression (dB)
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PCB Design Requirements
PCB Surface Finish The PCB surface finish used for RFMD's qualification process is Electroless Nickel, immersion Gold. Typical thickness is 3inch to 8inch Gold over 180inch Nickel. PCB Land Pattern Recommendation PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. PCB Metal Land Pattern
A = 0.69 x 0.28 (mm) Typ. B = 0.28 x 0.69 (mm) Typ. C = 3.40 (mm) Sq. 3.50 (mm) Typ. 0.50 (mm) Typ.
Pin 32
B
Pin 1
B
B
B
B
B
B
B
Pin 24
A 0.50 (mm) Typ. A A A C A A A A 0.63 (mm) Typ. B B B B B B B B
A A A A A A A A 1.75 (mm) Typ. 3.50 (mm) Typ.
Pin 16
0.63 (mm) Typ.
1.75 (mm) Typ.
Figure 1. PCB Metal Land Pattern (Top View)
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RF2958
PCB Solder Mask Pattern Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB Metal Land Pattern with a 3mil expansion to accommodate solder mask registration clearance around all pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be provided in the master data or requested from the PCB fabrication supplier.
A = 0.79 x 0.38 (mm) Typ. B = 0.38 x 0.79 (mm) Typ. C = 3.55 (mm) Sq. 3.50 (mm) Typ. 0.50 (mm) Typ.
Pin 32
B
Pin 1
B
B
B
B
B
B
B
Pin 24
A 0.50 (mm) Typ. A A A C A A A A 0.63 (mm) Typ. B B B B B B B B
A A A A A A A A 1.75 (mm) Typ. 3.50 (mm) Typ.
Pin 16
0.63 (mm) Typ.
1.75 (mm) Typ.
Figure 2. PCB Solder Mask Pattern (Top View) Thermal Pad and Via Design The PCB Metal Land Pattern has been designed with a thermal pad that matches the exposed die paddle size on the bottom of the device. Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results.
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